Education

University of Bristol

September 2017 - June 2021

Master of Engineering in Electrical & Electronic Engineering

1st Class Honours (74%)

Thesis: “A novel make-up gain stage for the software-based Moog 4-pole audio filter” (Achieved 72%)

• Projects: loudness-restoring audio plugin based on ITU-R BS.1770, Rubik’s Cube solving robot, FPGA peak byte generator/detector, DSP-based Goertzel algorithm implementation, embedded SoC/bridge design, LDPC coding system simulation, real-time autonomous robot programming

• Units: Digital/Analogue Electronics & Filters, Embedded Real-Time & VLSI System Designs, Networking Protocols & Applications, Mobile Communications, Sustainable Power Engineering, Audio & Image Processing

• Achieved 70% in First Year, 70% in Second Year, 74% in Third Year, 75% in Fourth Year

Work Experience

Arm Ltd

Cambridge, United Kingdom

Verification Engineer

October 2022 - Present

• Verification lead on a message-collating sub-component that outputs messages from PCIe endpoints to the Generic Interrupt Controller (GIC) as part of the next generation of GIC. Responsibilities include developing the testbench from scratch, and coordinating functional verification on the block.
• Developed a model of an internal functional safety-compliant error-collecting unit/block for our formal verification methodology, as part of our ongoing functional safety drive for automotives, in addition to writing directed and block/top-level test sequences to test its register models and error/response-reporting capabilities.
• Utilized UVM and SystemVerilog’s functional and class-based coverage to analyze our component’s multi-chip configuration and a ACE/AXIT translation interconnect, and made decisions on coverage waivers.

Graduate Verification Engineer

August 2021 - October 2022

• Collaborated on-site & remotely with engineers on significant projects within rotational teams, including implementation of a novel method to verify results of various protocol checkers, data transfers, and mass regressions - utilised in the latest releases of functional safety-compliant interrupt controllers.
• Implemented a framework using machine learning models to reduce number of seeds required to achieve the same regression coverage, and automated the pipeline for various testplans.

Image Signal Processing (ISP) Hardware Verification Intern

June 2020 - September 2020

• Collaborated with an external division within Arm to obtain metric processing scripts on Python, and developed a database system to store parsed information, with scalability & user experience considered.

Technical Skillsets

• Experience in development of testbenches and end-to-end functional verification of sub-components and an overall system that adheres to both architecture and micro-architecture, and development & writeup of specifications

• Experienced in embedded SoC development with V/SV/VHDL/C/C++ utilising QuestaSim & Xilinx ISE, and verification methodologies including UVM, formal verification

• Adept in object-oriented programming concepts, general data structures & algorithms, version control with Git, CRUD systems, and web/software development in HTML/CSS, Python/JavaScript, and MATLAB

• Capable with advanced electronics concepts, circuitries & operations, including System-on-Chip & bridge design, digital & analogue circuit design, and able in communication system concepts (including mobile) and network principles

• Previous experiences with microcontrollers and its languages in personal, internship & university-related projects, i.e. Arduino, Raspberry Pi, TI LaunchPad

Proficiencies

Problem Solving & Creativity

• Used an OOP-based approach (with SystemVerilog class handles) to verify a novel message-collating sub-component in the next generation of GIC. Despite initial pushbacks and risk of confusion, this method uses the full extent of SystemVerilog’s OOP capabilities not previously seen in GIC’s past projects, and allowed for cleaner and more accurate verification of the block, especially when architectural compliance must be upheld.
• Developed a methodology for collecting coverage data from functional verification & image quality metrics given top-level specifications with Python & SV as part of my Arm internship and graduate schemes, and designed database methods for storing & querying the collected information.
• Using a new in-house machine learning framework, prototyped a novel method of reducing number of regressions required to achieve the same percentage of functional coverage.
• Designing & fabricating a Rubik’s Cube puzzle-solving robot from minimal requirements, with concerns to resource efficiency, performance, design choices, longetivity, and output verification.
• Programmed a PNM to PGM conversion (and vice versa) in C & an FPGA byte generator/detector in VHDL from minimal specifications, and programmed a disease/population analysis program in Python.

Proactivity & Preparedness

• Researched multiple approaches to building verification of a block, as part of being the verification lead on a new message-collating sub-component within GIC. Eventually settled on a OOP-based approach using class handles to ensure ordering with consideration of information visibility between two separate I/Os in a system, with reasonable justification and planned mitigations to reduce confusion in specifications.
• Took executive decision, with justification for time, to reduce test cases required to verify a bugfix of a cross-system GIC implementation, as a result of encountering overly-random testing scenarios. Sufficient signoff undertaken & product was released on-time.
• Applied Git version control to our FPGA Digital Design & Embedded SoC Design Group Projects, and updated the repository daily. Backups are readily available & restored during occasional incidents, resulting in minimal work lost.

Communication & Collaboration

• Developed the testbench and verification specifications for a novel message-collating sub-component within GIC. Asked for feedback on multiple iterations to ensure concise statements whilst retaining sufficient information, and guaranteed that all diagrams are visible despite color-blindness.
• Presented my Arm internship and rotations’ project proposals to members within Functional Verification and System IP teams. Organised project scope, approaches, and results into concise presentation topics.
• Developed communication skills & techniques essential to explaining difficult engineering concepts for children & students in the OutReach programme, including learning & understanding each individual’s needs.

Teamwork & Leadership

• Verification lead on a message-collating sub-component that outputs messages from PCIe endpoints to the GIC as part of the next generation of GIC. Developed the block’s testbench from scratch, and coordinated functional verification on the block alongside the block’s designer and formal verification engineer. Current knowledge source of the block’s behaviors.
• Ownership of top-level end-to-end testing of the safety-compliant GIC - coordinated implementation of testing suites as part of GIC’s safety-compliant release signoff.
• Spearheaded Arm’s initiative of IET Partnership, alongside my mentor, and propelled a drive for engineering chartership within the community.

References available on request